05/07 Vishal
HR at End 2 End Catalyst

Views:162 Applications:16 Rec. Actions:Recruiter Actions:2

IP Verification Engineer - System Verilog/UVM/RTL Design (3-10 yrs)

Bangalore Job Code: 339521

Desired Skills and Experience :

- 3 - 10 years- experience in Design Verification

- Excellent Communication and Presentation Skills

- Strong System Verilog or Specman expertise OVM/UVM/eRM expertise highly desired

- Good knowledge of protocols

- Ability and desire to learn new methodologies, languages, protocols etc

- Front-End Design and Verification

- Architecture design, RTL Design, Chip Integration, Testbench Creation, Testplan and Test vector coding, Assertions, SVA, Functional Coverage, Verilog, VHDL, System Verilog with OVM/ UVM/ VMM, IP Verification, SOC Verification, Functional and Timing Simulations, Power Aware simulations, CPF/ UPF based verification, AXI

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