29/07 Tulsi Arora
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IP Verification Engineer - System Verilog (5-10 yrs)

Bangalore Job Code: 473668

Our leading clients provide end-to-end support for the semiconductor industry.

They are looking for IP Verification to be based at Bangalore with the following skills :

- Total 5 - 10 years of experience in IP Design Verification

- System Verilog or Specman expertise OVM/UVM/eRM expertise highly desired

- Must have strong knowledge of protocols

- Ability and desire to learn new methodologies, languages, protocols etc

- Notice Period: 30 days or serving 60 days or 90 Day notice period

- Education: BE/BTech, ME/MTech ( VLSI Domain )

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