IP/SOC Design Lead - ASIC Digital Design & Verification (8-17 yrs)
IP/SOC Design Lead
- Master Degree from a renowned school.
- 10+ years effective experience in ASIC digital design and verification.
- Shows good understanding of place and route flow.
- Able to look beyond the current block to design and take the full system performance into account.
- Has experience with mixed signal designs and working with analog designers.
- Experience with functional validation on silicon is nice to have.
- Expert in VHDL and Verilog
- Has good knowledge of System Verilog/UVM
- Has good scripting capabilities : TCL, Python, Perl)
- Familiar with Cadence and/or Mentor simulators : (ex irun, ncsim, vmanager, questa, modelsim)
- Familiar with EDA tools such as : Formality, conformal, Dc compiler, RTL compiler, primetime)
- Familiar with ATPG tools (ex : tetramax, tessent)
- Has experience with version control (ex : Subversion, Git, DesignSync, Cliosoft)
- Has experience with bug reporting tools (ex : JIRA, Collbanet, Trac, Bugzilla)
- An analytical mind and strong commitment to quality is necessary with experience in following design methodology guidelines.
- Has good team spirit, open minded, friendly, self-evaluating and having a great sense of responsibility.
- Proven experience in team management with good schedule build and follow up skills .
- Experience with remote (European) teams/management is a plus.
- Strong communication skills.