04/10 Priyanka
Technical Recruiter at Infinity HR

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IP Design & Verification Engineer - Mixed Signal/RTL Design (2-10 yrs)

Noida Job Code: 367699

Position : Design Engineer - IP Design & Verification

Job Description :

Role :

- Involved in Front-End IP Design and Verification related to Analog and Mixed Signal IPs. Apart from the obvious challenge of First-time right, functionally accurate and robust, other challenges include complying Verilog/AMS, SV-UVM standards, striving for zero defects, etc

Job Details :

The incumbent will be Involved in Front-End IP Design and Verification related to Analog and Mixed Signal IPs. Apart from the obvious challenge of First-time right, functionally accurate and robust, other challenges include complying Verilog/AMS, SV-UVM standards, striving for zero defects, etc

Must have skills:

- Concepts of RTL and DFT design.

- Should have good understanding of Verilog/VHDL/SV-UVM.

- Knowledge of Tcl and Perl scripting.

Good to have skills :

- Adaptable, Flexible, Global Approach, creative and capable of working independently as well as a team player.

- Should have a strong sense of urgency. Solutions orientation; Quality driven; Execution minded; Customer focused

- Work Experience : 2-8 years

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