Researcher at New Era India
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IP/ASIC/SOC Verification Engineer - UVM (2-15 yrs)
Job Responsibilities :
- Verification of key digital blocks and SoCs in processor core based complex SoC products
- Define testplan, tests and verification methodology for block and chiplevel verification.
- Architect the testbench and develop in UVM or Formal based verification approaches. Integrate the block testbench at chiplevel UVM environment and verify integration.
- Work with design team in generating test-plans and closure of code and functional coverage. The job also needs continuous interaction with analog co-sim and firmware team in enabling toplevel chip verification aspects.
- Support post-silicon verification activities of the products working with product evaluation and applications engineering team.
Position Requirements :
- BTech/MTech degree in Electrical/Electronics/Computer science from reputed institutes
- Experience in design verification with UVM and constrained random, coverage based verification approaches.
- Knowledge of Assertion based formal verification will be a plus
- Good verbal and written communication skills to work effectively with teams spread geographically
- Good debugging and analytical skill