23/10 Priyanka Reddy
HR Executive at Swedium global

Views:152 Applications:5 Rec. Actions:Recruiter Actions:1

Indium Global Services - ASIC Verification Engineer - RTL/SoC/System Verilog (7-10 yrs)

Overseas/International/EU/Sweden Job Code: 373489

Position 1. : Verification- Sweden/Finland

Mandatory Skills :

- Experienced System Verilog verification engineer

- Gate level simulation experience

- Structured, self-driven, flexible

- Scripting in Perl, Python, Bash or C-shell

- Good skills in working with UNIX and/or Linux

- At least 7+ years in ASIC industry

Meritorious Skills :

- Power estimation experience

- Low power RTL+UPF simulation and verification

- Experience on defining works flows and new ways of working

- Clearcase version control system experience

- UVM verification methodology

- VHDL knowledge

- More than 5 years in the ASIC industry

Position 2. : ASIC Verification - Sweden/Finland

- A strong experience in ASIC verification- IP or SOC.

- experience in System Verilog and UVM Methodology based verification or c driven verification or Specman e.

- Minimum of 5+ Years of VLSI Verification experience.

- Good command on English both in written and spoken, Swedish language knowledge is an advantage

- You should have Positive attitude, social skills, a desire to help team members, structured way of working and an eye for quality work.

- You enjoy working both independently and in a small diverse and you are focused on reaching result on time.

- The work will be carried out in a cross functional team using Scrum/Agile ways of working

- Experienced in WCDMA, GSM and/or LTE systems (preferred).

Position 3. : ASIC Verification-Sweden

- Good knowledge of the industry's image processing, crypto, and DMA with 5 years at least

- Verification is at the module level, constrained random, VMM / UVM, reference models in the TLM / SystemC

- A resource gap for both verification and design are the team that makes the post-processing of the image processing. They model (SystemC / TLM), design (System Verilog) and verifies (System Verilog / UVM).

- Team is working agile with backlogs, stories and daily syncs.

- Another resource gap is in a DMA module for crypto, mostly involves the updating of an existing design.

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