05/08 Nandini S
Lead IT Recruiter at Amisign Technologies

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Functional/ASIC Verification Engineer - System Verilog/UVM (7-20 yrs)

Pune Job Code: 476904

Requirements :

- SATA Protocol knowledge and experience.

- Knowledge and experience with Flash, I2C and UART protocols.

- Experience developing complex random verification environment using System Verilog/UVM/OVM/VMM/Vera

- Experience with writing and execution of detailed verification test plan.

- Experience with scripting language such as Python or Perl and EDA Verification tools, as well as bug tracking and regression mechanisms.

- Experience with object-oriented design and implementation.

Preferred/Plus :

- Hands on knowledge of ARM processor based subsystem verification

- Experience with Gate Level Simulations

- Working knowledge of C/C++ and ARM Assembly programming.

- Familiarity with Post-Silicon validation and debug.

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