Full Chip Verification Engineer - VLSI/Verilog/UVM (4-10 yrs)
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Full Chip Verification Engineer - BLR / Noida / Hyd / Malaysia
Qualification: BTech / Mtech / BE / ME
Experience Level : 5-10 yrs
Job Description : FCV verification.
- Good verification skills (Verilog, system Verilog)
- Well versed with digital design fundamentals
- Knowledge of UVM methodology.
Verification Engineer - BLR / Noida / Hyd / Malaysia
Job Description :
Verification of IP blocks
Qualification : B.Tech or M.Tech in Electrical or Electronics Engg
Experience Level : 5-7years
Basic Job Deliverable :
- Develop UVM test bench for IP blocks
- Write and execute test cases
- Work on the closure of functional and code coverage
- Experience in the verification of CPU/Video/DSP/vector processors, SIMD, etc. is preferred
- Strong foundation in SoC architecture and verification of multi-core processors including SIMD, Vector processors, floating point, etc. is a plus
- Expertise in Verilog/System Verilog, C/C++/SystemC, UVM, Scripting languages like Perl/Python, etc.
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