12/04 Neha Kukde
HR Executive at Swedium Global Services AB

Views:241 Applications:14 Rec. Actions:Recruiter Actions:7

FPGA Verification Engineer - VHDL/System Verilog (4-12 yrs)

EU Job Code: 432841

Skill set required :

- Familiarity with modern FPGA device families and tools.

- Deep knowledge of SystemVerilog, UVM/OVM, and SVA.

- Experience with scripting languages and tools (TCL, Python, Perl, Make).

- Analytical mindset, high capacity, results oriented and the ability to deliver under pressure.

- Excellent English verbal and written communication skills.

- A highly motivated self-starter, able to work independently, while being a team player.

- Bachelor's degree in a relevant discipline, with demonstrated experience and knowledge in the above mentioned required skills areas.

Additional Expertise :

- Some knowledge of wireless systems and 3GPP specifications will be highly appreciated.

- Knowledge of Digital Signal Processing, DSP modeling.

- Experience with hardware realizations, and bit-exact verification techniques.

- Experience using Matlab or similar tools for mathematical analysis

- Experience in RTL design targeting FPGAs using SystemVerilog/Verilog/VHDL.oops concepts

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