30/07 Pallavi Joshi
Director at Beafirm Infotech Private Limited

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FPGA Lead - RTL Design & Development (5-10 yrs)

Bangalore Job Code: 474697

Required Skills :

- Experience in RTL design, development, simulation, validation (Verilog, System Verilog)

- Block level and SoC level design and simulation

- Ability to develop designs from specification right through to gate level simulations

- Proficient with EDA simulation tools (Questa)

- Good knowledge in hardware architecture and design cycle flow

- Experience in design with FPGAs (Zynq Ultrascale+), I/O planning, Power estimation etc.

- Good understanding of High-Speed Interfaces & Protocols as PCIe, 10G/40G Eth, CPRI, JESD204B, Aurora etc.

- Experience in implementation of wireless communication modules in FPGA

- Experience in memory interfaces DDR3/3L, DDR4 component and DIMM

- Experience in board bring up and good debugging skills

- Aware of optimization techniques (Resource, Power & Timing)

- Design experience using PLLs, Clocks, ADCs and DACs. Timing synchronization protocols like 1588, GPS added advantage

- Experience with test equipment's like DSO, MSO, Logic analyzer.

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