Semiconductor Recruiter at Swedium Global Services
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FPGA Design Engineer - VHDL/Verilog (5-7 yrs)
Job Requirement :
- Experience in working with FPGA Design for 5 years at least
- Synthesis this to VHDL/Verilog code for using in an FPGA.
- Writing logic code by using either VHDL or Verilog.
- Matlab and Simulink knowledge is highly appreciated.
- Xilinx toolchain for simulation and all related activities
- Should be a team player
- Should be hands on person and ready to work individually
- This is for long term project in Sweden and hence ready to relocate within 2 months of time