09/10 Manish Dutta
Team Lead Recruitment - IT at Skyleaf Consultants

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FPGA Design Engineer - VHDL/RF Design (4-10 yrs)

Noida Job Code: 369369

- 4+ years of experience with RF design using Verilog or VHDL for Xilinx FPGAs

- Experience with DSP flows for simulation software, including Vivado and MathWorks MATLAB, Simulink

- BA, BS, or BE degree in Electrical Engineering, Computer Science, or a related field


- Define and architect high-performance FPGA blocks that power our Software Defined Radio (SDR)


- Manage project priorities, deadlines, and deliverables


- Implemented serial interfaces SPI, I2C, and UART.


- Worked on PCIe Express interface for PIO and Bus Master DMA based designs in FPGA.


- Implemented GTX interface for board to board high speed communication.


- Implemented LVDS 7:1, 4:1, 8:1 serialization and de-serialization interface using OSERDES and ISERDES and IODELAYs.


- Worked on TCP & UDP implementation in VHDL in FPGA and MAC to MAC interface in FPGA.


- Worked on DDR3 interface in multiple projects and implemented DDR3 User interface over AXIFull.


- Worked on external memory interfaces like Asynchronous SRAM, Synchronous SRAM, Parallel NOR Flash and EMMC NAND Flash in multiple Video based projects.


- Worked on multiple low speed serial ADC and DAC, parallel ADC and DAC, and Hi speed ADC & DAC chips with LVDS DDR lines in multiple projects.


- Implemented Video DAC (VGA) interface with H-sync, V-sync and with embedded sync and blank in RGB and composite video modes with multiple resolutions like 640x480, 1280x1024, 1920x1080, 1920x1200 etc.


- Interfaced HDMI, PAL Encoder and Decoders chips with FPGA in multiple projects.


- Implemented SD-SDI with LVDS interface and SD-SDI & HD-SDI using GTX.


- Implemented USB 2.0 and USB3.0 with Cypress & FTDI chips.


- Implemented various DSP algorithms (filters, modulations, freq-hopping .etc) in MATLAB.


- Expertise in implementing DSP models in SIMULINK using tool boxes like ALTERA DSP BUILDER, XILINX SYSGEN.


- Implemented various DSP algorithms in Verilog like FM demodulations, Peak Search, Automatic Gain Controller, and Hilbert Transform.


- Complete Digital Down Conversion (DDC) chain implemented inside FPGA with combination of NCO, MIXER, FIR, & CIC algorithms.


- Simulated signal processing of the complete Wideband & Narrowband Receiver chain in Matlab Simulink.


- Experience in FPGA interface with various and Clock Synthesizers, Audio Codec's and I2C EEPROM devices.


- Implemented Ethernet Protocol using NIOS processor in CYCLONE FPGA.


- Implemented Custom components for Q-sys using Avalon interfaces.


- Implemented various custom components using AXI-FULL, AXI-Stream, AXI-lite interfaces bus interfaces.


- Hands on experience with embedded processors like Black fin DSP processor, NIOS-II and ARM processor.


- Expertise in ZYNQ FPGA - Soc based Architecture based designs.

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