25/07 Neha Kukde
HR Executive at Swedium Global Services AB

Views:386 Applications:26 Rec. Actions:Recruiter Actions:10

FPGA Design Engineer - MATLAB/Simulink (4-16 yrs)

EU Job Code: 345880

- Candidate should have experience in development in Matlab (signal processing) and synthesis this to VHDL/Verilog code for using in an FPGA.

- Experience in working with FPGA Design for 5 years or more

- Writing logic code by using either VHDL or Verilog.

- Matlab and Simulink knowledge is highly appreciated.

- Xilinx toolchain for simulation and all related acvities

- Should be a team player

- Should be hands on person and ready to work individualy

- This is for long term project in Sweden and hence ready to relocated within 2 months of time

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