HR Executive at Swedium Global Services AB
Views:395 Applications:27 Rec. Actions:Recruiter Actions:10
FPGA Design Engineer - MATLAB/Simulink (4-16 yrs)
- Candidate should have experience in development in Matlab (signal processing) and synthesis this to VHDL/Verilog code for using in an FPGA.
- Experience in working with FPGA Design for 5 years or more
- Writing logic code by using either VHDL or Verilog.
- Matlab and Simulink knowledge is highly appreciated.
- Xilinx toolchain for simulation and all related acvities
- Should be a team player
- Should be hands on person and ready to work individualy
- This is for long term project in Sweden and hence ready to relocated within 2 months of time
This job opening was posted long time back. It may not be active. Nor was it removed by the recruiter. Please use your discretion.