23/08 Madhavi
BDM at Rishyaa Digicorp

Views:800 Applications:59 Rec. Actions:Recruiter Actions:22

FPGA Design Engineer - ASIC/RTL/System Verilog (3-6 yrs)

Bangalore/Chennai/Hyderabad Job Code: 483823

Job Description :

ASIC/FPGA Designer Profile :

- Extensive experience in RTL coding using Verilog, System Verilog and VHDL

- Extensive domain knowledge

- Switching,

- Signal processing,

- High speed serial I/F

- RTL simulations and debugging

- Implementation of test cases for verification

- Experience from Logic synthesis

- Expertise in Verilog Hardware Description Language.

- Good fundamentals of logic design and RTL coding.

- Experience in synthesis and timing closure.

- Individual ownership of standalone FPGA designs.

- Support for HW board bring-up.

- Working knowledge of lab equipment such as oscilloscopes and logic analyzers.

Desired experience :

- Knowledge of scripting languages.

- Working knowledge of 1000/100/10M Ethernet.

- Experience designing FPGAs with embedded soft or hard processors.

- FPGA implementation of closed loop control systems.

Women-friendly workplace:

Maternity and Paternity Benefits

Add a note
Something suspicious? Report this job posting.