Director - Digital Physical Design (12-16 yrs)
In this role :
- You will be leading a team of engineers in an effort to collaborate with architecture, CAD, timing and logic design teams, with a critical impact on delivering best in class PHY designs.
- You will be required have hands-on experience in delivering the best in class PHY design.
Responsibilities and Duties :
- You will be involved with all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.
- Your responsibilities include but are not limited to leading and managing a team of engineers to generate block/chip level static timing constraints.
- See through full chip floor-plan including pin placement, partitions and power grid.
- Develop and validate high performance low power clock network guidelines.
- Perform block level place and route and close the design to meet timing, area and power constraints.
- Generate and Implement ECOs to fix timing, noise and EM IR violations.
- Run Physical design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers. Participate in establishing CAD and physical design methodologies for correct by construction designs.
- Assist in flow development for chip integration.
Required Experience, Skills and Qualifications
- You will have at least 12+ years of Physical Design experience on high PHY and/or SOC designs
- You will have at least 5+ years of management experience and leading a team in delivering products. Experience in collaborating with front-end and backend teams is huge plus
- Deep knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route
- Significant hands-on experience in developing and implementing Power-grid and Clock specifications
- Deep Understanding of all aspects of Physical construction, Integration and Physical Verification
- Deep knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic design team for timing fixes.
- Power user of industry standard Physical Design & Synthesis tools
- Deep understanding of scripting languages such as Perl/Tcl
- Extensive knowledge of Extraction and STA methodology and tools
- Deep understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level
Education & Experience : Preferred Masters or PhD Degree. Bachelors Degree in technical discipline required.