IT Recuriter at Infinity HR
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Digital Design Verification Engineer - System Verilog (8-15 yrs)
- 8+ years of DV experience in building and architecting verification environments, preferably from scratch for multiple projects.
- The engineer should have experience in writing testplan, creating & enhancing verification environments and be comfortable coding any portion of a test bench (models, checkers, scoreboards, coverage monitors, etc.).
- Candidate should have experience in the development of constraint random DV environments for large ASIC blocks.
- Languages: Must have experience in Verilog/SystemVerilog.
- Experience with C++ is a plus.
- Methodology: Strong UVM (must) and Specman (is a plus).
- Experience with gate level simulation and debug.
- Scripting: Perl, Python.
- Experience with PCIe and/or networking (Ethernet) protocol is a plus.
- Experience with SoC verification is a plus.
- Good interpersonal/communication skill.
- Experience in assertion methodology, emulation/hardware accleration platforms is a plus.