Director at Core Edge Solutions
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DFT Lead - ATPG/LBIST/Physical Design (5-10 yrs)
Job Description :
- Design For Test (DFT) Engineer with experience in all aspects of test for deep sub-micron ICs (40nm and smaller).
- Duties will include test planning for large digital SoC devices, scan insertion, ATPG, test pattern development and silicon debug of test patterns.
- Technical interaction with both physical design and test engineering teams will be required. Candidate should have hands-on experience generating and validating ATPG patterns for large digital SoCs. Experience with implementation of Logic BIST (LBIST) for in-system test is also required. Strong scripting ability is required with specific expertise in PERL, TCL and TK languages.
- Develop, implement and verify state-of-the-art Design for Test (DFT) architectures. Must have at least one block level architectures experience.
- Work with block designers to integrate DFT implementations
- Work with physical design team to setup and implement DFT insertion flow
- Strong project management and communication skills will be needed. Work with remote virtual teams may be required.
- At times, candidate may need to participate in teleconferencing at late evening and early morning times.
- Additionally, a working knowledge of IEEE 1149.1/1149.6 standards and experience in BSDL creation and validation is desired.
- Desired EDA Tool experience: Mentor Graphics TestKompress, Synopsys DFTMax & Tetramax, Cadence ET and/or Modus
Coding languages : PERL, TCL, and TK
Experience : 6-10 years
HSR - Bangalore