09/04 A.Recruiter
Recruiter at Shellinfotech

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DFT Engineer - Verilog/System Verilog (3-12 yrs)

Bangalore/Chennai Job Code: 431422

JD :


- Fundamentals of SCAN stuck-at and at-speed techniques.

- Expertise in handling Mentor Graphics EDT logic.

- Knowledge on On chip clock controller (OCC).

- Pattern generation with Mentor Graphics TestKompress Tool.

- Good knowledge in BSCAN operations. Knowleedge in MBIST Operations.

- Expertise in handling Synopsys SMS tool sets (Integrator, Builder, Yield Accelerator).

- Excellent track of pattern simulation and coverage analysis (preferred cadence ncsim simulator expert Experience in ATPG, Scan, BIST and Mentor TestKompress.

- Expert in writing test benches (Verilog, system Verilog) and tests for different components like PLL, ADC etc for generating ATE vectors.

- Experienced engineers with DFT flow, ATPG, Scan, BIST and Mentor TestKompress.

- Experience with the mentor tool sets.

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