05/12 Shankar
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DFT Engineer - Verification (1-4 yrs)

Chennai Job Code: 387819

Current requirements include activities involving :

- Digital/mixed-signal optimal DFT architecture definition rationalizing across test time/cost, coverage, dppm and customer quality

- Plan DFT activities for self and the team

- DFT logic integration and verification

- Achieve coverage metrics

- DFT automation and methodology

- GateLevel DFT verification

- Pattern generation, verification and delivey

- Post silicon bringup and production support

Roles & Responsibilities :

Looking for suitable hands-on engineers with experience in SOC/IP/Sub-System DFT.

- Technical leader who can assimilate customer requirements and help device execution plans

- Responsible and accountable with pro-active communication skills and a proven track record

- Strong technical contributor

- Work in a team environment

- Able and willing to provide technical mentorship to team members.

- Support periodic training session and knowledge sharing sessions.

- Should be able to work across cultural/functional/geographic boundaries

- Experienced in of all the aspects relating to :

1. Scan/ATPG

2. Scan synthesis, coverage metrics by fault-models - stuck-at, delay & Bridging,

3. Memory BIST

4. Test Mode STA

5. Test power estimation, Boundary Scan, IDDQ, IO testing, Mixed-signal IP testing, Analog IP testing

- Expert in EDA tools

- Strong debug skills and automation savvy.

- Post-Silicon debug and support

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