Director at Nastech Consulting
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DFT Engineer - Semiconductors Domain (3-7 yrs)
Job Desription :
- DFT architecture definition w.r.t. test time/cost, coverage, test power.
- Good experience/concept on all aspect of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan.
- DFT logic integration and verification.
- Experience on debugging low coverage.
- Gate Level DFT verification with and without timing.
- Pattern generation, verification and delivery to ATE team.
- Post silicon debug and support on failing patterns.
- Experience of leading small DFT team is plus.
- Good experience on EDA tools of reputed vendor like Mentor, Synopsis.
- LBIST experience is plus.
- DFT mode STA and timing closer support.
- Familiar to Verilog and RTL simulation.
- Strong knowledge and experience in Scan Insertion, TestKompression, ATPG, Memory BIST and JTAG at IC
- Level for mixed signal designs.
- Experience in using Mentor DfT tools, Cadence RC and simulator tools
- Define DfT Strategy and Requirement Specification for the design
- DfT verification for gate-level and timing simulations
- Work cross sites with design team to define and implement DfT.
- Hands on experience in solving DfT problems, simulation failures, ATPG coverage and DRC improvements.
- Work with STA engineer to define timing constraints for DfT modes
- Support Test engineer in silicon debug and pattern delivery for ATE
- Experience in RTL coding, shell scripting
- Experienced in handling analog DfT simulations