12/07 Rajalakshmi M
IT Recruiter at Infinity HR Consulting Pvt Ltd

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DFT Engineer - RTL/GDS/ATPG (5-15 yrs)

Bangalore Job Code: 467005

Duties :

As a DFT engineer, you will be responsible for design, implementation and verification of all aspects of DFT on complex IPs and chips at advanced process technology nodes viz. 14nm/10/7nm including :

- Test architecture definition

- Identifying and implementing RTL changes for DFT

- Developing constraints for scan insertion and test mode timing closure

- Scan and ATPG for different fault models

- MBIST implementation and verification

- Boundary scan, ACJTAG, IEEE 1500 implementation and verification

- IEEE1687 (iJTAG) and fault grading for functional manufacturing tests

- Running zero delay and timing simulations and debugging on all the above aspects

- You will be working on very high speed and low power designs.

Skills & Qualification :

- UG/PG with 3-8 years of relevant work experience and strong understanding of DFT concepts

- Strong hands on Experience using industry standard EDA Tools

- Experience with logic simulators from one or more EDA vendors

- Experience on Mentor Tessent tools and Cadence Modus Test tools

- Experience with RTL lint tools like Synopsys Spyglass

- Experience in scan insertion, coverage analysis and debugging skills on faults coverage enhancement is required

- Exposure to RTL2GDS flow and tasks such as synthesis and scan insertion, STA and IR drop

- Experience in post silicon validation, ATE debug and support is desired

- Good understanding of Logic design, RTL implementation & verification, logic synthesis, Logic Equivalent Checking & Static Timing Analysis is a plus

- Experience on multiple complex chips at different technologies like 14nm/10/7nm etc

- Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability

- Programming in Perl, Tcl or other scripting languages is a plus

Women-friendly workplace:

Maternity and Paternity Benefits

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