DFT Engineer - Mixed Signal (4-8 yrs)
Role : DFT Engineer
The candidate is expected to have worked on :
- Scan insertion and DRC cleanup
- Pattern generation for Stuck-At, delay test, iddq, path delay and fault grading.
- Memory testing. Should also know the algorithms.
- Should also have knowledge about diagnostics. JTAG or P1500 or other interface mechanism.
Desirable competencies :
The candidate is expected to have exposure to :
- Compression tools is highly desirable
- LBIST, mixed-signal testing, logic equivalence
- Writing test benches and should be capable of writing RTL code for DFT blocks as and when required.
- Bridge fault detection is desirable
- ATE experience is an added advantage.
Education : BE/ BTech (Electronics/ Electrical/ Electronics and Communication) MS or MTech would be preferred