11/06 Kamal D
Senior Career Consultant at Teamlease

Views:217 Applications:9 Rec. Actions:Recruiter Actions:1

DFT Engineer - ATPG/Verification/ATE (3-5 yrs)

Bangalore/Hyderabad Job Code: 332631

DFT Engineer requirement with our client in Bangalore & Hyderabad

Core Description : Responsible for SCAN, MBIST, JTAG, Vector generation and Verification and ATE post-silicon debug for complex 28nm and 22nm SoC.

Experience : 3 - 5 Years

Job Location : Bangalore and Hyderabad

Mandatory Skills :

- Experience in Scan insertion & Compression, Pattern Generation and Validation.

- Expereince in Boundary scan, LBIST, MBIST, JTAG and Low Power DFT atChip level and IP level

Tools : Fastscan/ TestKompress /DFTCompiler/ DFTMax/ DFTAdvisor/ TetraMax.

Desired Skills :

1) In depth knowledge and hands on experience in scan insertion, MBIST insertion and Memory Validation, ATPG, coverage analysis, Transition delay test coverage analysis.

2) Understand ATPG failures, debug or resolve DRC issues, Chain trace issues, Debug and Fix gate level Pattern simulation issues, both No-Timing and Timing simulation.

3) Knowledge of IDDQ constraints generation and validation and silicon bring up and debug.

4) Expertise in scripting languages like PERL,Shell etc

Educational Qualifications : BE/BTech/ME/MTech Electronics / Electrical/ Computer Science Engg

This job opening was posted long time back. It may not be active. Nor was it removed by the recruiter. Please use your discretion.

Add a note
Something suspicious? Report this job posting.