DFT Engineer - ASIC/SoC/Verification (5-10 yrs)
Groups GFX blocks to generate GFX tiles for synthesis.
- Run CDC/Lint tool to check RTL code quality.
- Run synthesis regression to monitor GFX tile/block status.
- Synthesis and deliver netlist that meeting timing, area and power requirement. Resolve formality.
- Lint and CDC issue. Help PD on the floor planning and close timing. - Scan insertion, Memory Bist insertion and verification.
- Signoff Full chip timing
Education& Qualifications :
1. Candidate is preferred to be MSEE with minimum of 3 years, or BSEE with minimum of 5-year experience in digital ASIC/SOC synthesis/DFT/integration field.
- Familiar with SOC/ASIC chip develop flow
- Familiar with front-end EDA tools and flows
- Familiar with Verilog/SystemVerilog programming and unix/linux and scripts (tcl, perl etc.)
- Fluent English on talking, presentation and writing documents.
- Work is performed with limited supervision. Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
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