08/06 Anitha
HR at Clavius Solutions

Views:130 Applications:4 Rec. Actions:Recruiter Actions:1

DFT Engineer - ASIC/SoC/Verification (5-10 yrs)

Anywhere in India/Multiple Locations Job Code: 332219

Responsibilities :

Groups GFX blocks to generate GFX tiles for synthesis.

- Run CDC/Lint tool to check RTL code quality.

- Run synthesis regression to monitor GFX tile/block status.

- Synthesis and deliver netlist that meeting timing, area and power requirement. Resolve formality.

- Lint and CDC issue. Help PD on the floor planning and close timing. - Scan insertion, Memory Bist insertion and verification.

- Signoff Full chip timing

Education& Qualifications :

1. Candidate is preferred to be MSEE with minimum of 3 years, or BSEE with minimum of 5-year experience in digital ASIC/SOC synthesis/DFT/integration field.

Experience :

- Familiar with SOC/ASIC chip develop flow

- Familiar with front-end EDA tools and flows

- Familiar with Verilog/SystemVerilog programming and unix/linux and scripts (tcl, perl etc.)

- Fluent English on talking, presentation and writing documents.

- Work is performed with limited supervision. Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.

This job opening was posted long time back. It may not be active. Nor was it removed by the recruiter. Please use your discretion.

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