09/12 Inder Jeet
Recruiter at 3x3conect

Views:146 Applications:24 Rec. Actions:Recruiter Actions:4

DFT Design Engineer - RTL/ATPG (2-7 yrs)

Bangalore Job Code: 388906

DFT Engineer

Location : Bangalore


Experience: 2-5 years


Job Description :

- Consultation for test solutions during design planning/budgeting.


- Test methodology design rules checking during RTL coding stages.


- Implementation of- design for test (DFT) compression, automatic test generation (ATPG) for single stuck at (SSAF), Transition Delay Fault, Cell-aware faults, and other advanced fault models


- Experience in- JTAG, MBIST, Scan Compression, ATPG, Fault Simulation.


- Experience with industry ATPG tools Synopsys Tetra MAX, Cadence Encounter Test or Mentor Fast Scan ATPG tools Synopsys DFT scan insertion.


- Experience with industry simulation tools such as- VCS, Modelsim, NC Verilog etc.


- Architect and implement solutions for built-in self-test (Memory and Logic BIST) circuitry to test devices in the field.


- Participation in customer's design and flow reviews.


- Diagnostics analysis and debug.


- Provides methodologies for test automation flow integration with design planning, RTL analysis, logic synthesis, physical design and sign-off verification tools (static timing, simulation, formal verification).


- Develops white-papers on methodology and other documentation as may be required for projects.


- Provides technical support/expertise for customers operating Synopsys test automation tools in a wide variety of application scenarios.


Provide technical leadership and Mentor other people in the team.

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