04/10 Dhamma Bhawsagar
Senior HR at Ams HR Pvt Ltd

Views:108 Applications:26 Rec. Actions:Recruiter Actions:13

DFT Design Engineer - Mixed Signal - VLSI Domain (1-7 yrs)

Bangalore Job Code: 266544

We have an urgent requirement for DFT Design for Testability for our leading MNC based in Bengaluru

Position : DFT Design for Testability

Exp : 1-7 Years

Location : Bengaluru

Notice Period : Immediate-30 Days

- DFT

Experience : 1 to 7 yrs

Qualification : BE/BTech, ME/MTech ( VLSI Domain )

Work Location: Bangalore

Job Description :

- Strong knowledge and experience in Scan Insertion, test compression, ATPG, Memory BIST and JTAG at IC - level for mixed-signal designs.

- Experience in using Mentor DfT tools, Cadence RC and simulator tools

- Define DfT Strategy and Requirement Specification for the design

- DfT verification for gate-level and timing simulations

- Work cross sites with a design team to define and implement DfT.

- Hands on experience in solving DfT problems, simulation failures, ATPG coverage and DRC improvements.

- Work with STA engineer to define timing constraints for DfT modes

- Support Test engineer in silicon debug and pattern delivery for ATE

- Experience in RTL coding, shell scripting

- Experienced in handling analog DfT simulations

- Be fluent with all common concepts of DfT and DfT tools

MB : 9405924876

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