22/02 Sonila Agrawal
Principal Talent Advisor at Ryte4u Solutions

Views:44 Applications:4 Rec. Actions:Recruiter Actions:4

Design Verification Lead - System Verilog/RTL/ASIC (10-15 yrs)

Chennai Job Code: 414751

JD :


- 10+ Years of Design Verification Experience (System verilog or Verilog)

- Familiar and well-versed with Industry standard Verification methodologies like coverage, OVM/UVM

- Development of Verification Plans interfacing with Design Teams

- Knowledge of System verilog Assertions and Formal Verification Techniques

- Self-Starter, having Excellent Analytical and Problem solving/Debugging skills

- Strong Communication and Interpersonal Skills with high ability to Root-Cause complex Technical issues and Ability to adapt to rapid and vibrant Environment with Dynamic Decision making skills

- Knowledge about Constrained random verification, Coverage Analysis

- Expert in using Verification Tools like VCS, Xcellium

- Strong programming and scripting skills like PERL, TCL, Shell scriptsh

- Expert Knowledge in checkers, coding SV Testbench, drivers, monitors, scoreboards, Independent Debugging skills

- Strong Experience in ASIC Design Verification flows and DV Methodologies.

- Self Motivated, creates Cohesive Vibrant Environment with Strong Team leading Skills

- Expert Knowledge in AHB, APB, AXI and other Bus protocols

- Experience in Verifying Designs at System level and block level using Constrained based Verification

- Experience with protocols like USB, I2C, SPI, PHY, SDIO,

- RTL, GLS & Co-Simulations & Coverage closure

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