25/07 Srilakshmi
IT Recruiter at Screative Software Solutions

Views:245 Applications:26 Rec. Actions:Recruiter Actions:4

Design & Verification Engineer - Verilog/System Verilog (3-11 yrs)

Bangalore/Chennai/Hyderabad Job Code: 345649

Role : Design and Verification

Experience : 3-11 Years

Location : HYD/BLR/Chennai

Client : Sivalley

Job description :

- Must have good knowledge on the verification flows

- Excellent hands-on debug skills and problem solving attitude.

- Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC

- Experience of working on Functional Verification, SoC Verification, Emulation

- Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language

- OVM/UVM Methodology knowledge and experience

- Must have good communication skills and the ability to work in a team environment.

- Preferably having experience in architecture such as x86 or ARM domain based SOCs

K Srilakshmi-HR Executive
Screative software services pvt.ltd,

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