12/07 Swati Singh
Team Lead at Apex SErvices

Views:227 Applications:20 Rec. Actions:Recruiter Actions:5

Design Verification Engineer - System Verilog/C (3-10 yrs)

Bangalore/Hyderabad/Noida Job Code: 466932

We have Urgent opening for DV/ DesignVerification for Hyderabad/Noida/Bangalore

Job Description :

Exp - 3+ yrs

Salary - Negotiable

NP - Immediate to 30 Days

- Good in IP/SoC verification

- Should be good in DV, with SV UVM knowledge.


- Experience in UVM based verification methodology. System Verilog

- Understanding and experience of SoC verification

- Exposure to Gate level simulations with sdf back annotation, good debugging skills

- Well versed with SV-UVM, Verilog, C, scripting experience for automation

- Familiarity with functional and code coverage

- Hands on experience with test bench development from scratch, test case coding and execution.

Women-friendly workplace:

Maternity and Paternity Benefits

Add a note
Something suspicious? Report this job posting.