24/11 Sureshm
Lead Recruiter at Kaizen

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Design Verification Engineer - System Verilog (4-12 yrs)

Bangalore Job Code: 383762

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Role : Design Verification Engineer


Location : Bangalore

Experience Level : 4-10 Years

Description :

- HVL - System Verilog - At least 3 years hands on experience.

- Verification methodologies - UVM/OVM - At least 3 years hands on experience.

- Hands on experience in developing assertions and checkers.

- Hands on experience in developing coverage plan and code/functional coverage analysis.

- Good problem solving/debug skills.

- SERDES/ Serial IP protocol knowledge is a plus.

- Knowledge of Industry standard protocols like Ethernet/PCIe is a plus.

Details Required :

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