04/05 naveen
Recruiter at BHRS

Views:291 Applications:30 Rec. Actions:Recruiter Actions:5

Design & Verification Engineer - System Verilog (3-7 yrs)

Bangalore/Hyderabad Job Code: 440096

Job Description

Good in programming: System Verilog, PLI/DPI interface, PERL/Shell script, C/C++, assembly language

- OVM/UVM Methodology knowledge and experience

- Excellent hands-on debug skills and problem-solving attitude

- Must have good knowledge on the verification flows

- Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC

- Experience of working on Functional Verification, SoC Verification, Emulation

Women-friendly workplace:

Maternity and Paternity Benefits

Add a note
Something suspicious? Report this job posting.