IT Recruiter at Infinity HR Consulting Services
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Design Verification Engineer - FPGA/System Verilog (4-14 yrs)
Design Verification Engineer
- B.E/B.Tech/B.S. or M.S/M.Tech in EE or CE with 6+ years of work experience
- Hands on experience with verification of System Verilog designs and usage of simulation tools/debug environments such as Synopsys VCS, Verdi tools.
- Strong understanding of state of the art verification techniques.
- Expertise in shell/PERL and other scripting tools.
- Excellent problem solving skills and willingness to think outside the box
- Excellent communication skills and experience working with global teams
- Experience as a verification engineer
- Understanding of various verification methodologies, tools and infrastructure for high performance IP and/or VLSI designs
- Exposure to FPGAs, FPGA programming, and FPGA software tool chain