DDR IO Char & Modelling Engineer - ASIC/VLSI/VHDL (5-10 yrs)
We have a requirement for DDR IO Char and Modelling
- Preferred Qualifications 5+yrs of relevant experience in DDR IO Modeling & Characterization
- Minimum Qualifications Bachelor's degree in Engineering, Information Systems, Computer Science, or related field
- 3+ years Hardware Engineering experience or related work experience
JD DDR IO char and modelling:
1. DDR IO characterization using Silicon Smart
2. IBIS model creation and verification
3. Creating views required for ASIC flows (e.g. Synopsys lib, LEF, Verilog Models)
4. View generation and verification
5. Drive and build automation with any of the scripting languages like Shell/Perl/TCL to improve the productivity and quality. Write behavioral models in Verilog/VHDL for the different flavors of IOs
6. Work with internal customers to understand the requirements and support the customers on behavioral models and timing models throughout the design cycle. Build verification plan and verify the design including both behavioral models and transistor level implementation for IO buffers.
7. Have circuit design knowledge in IO design and understanding of VLSI circuits and Spice simulator experience in finfet technology.