Talent Acquisition Leader at Cypress Semiconductor
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Cypress Semiconductor - STA Lead Engineer - Timing Analysis/Timing Closure (7-15 yrs)
- BE/BTech Electrical/Electronic or ME/MTech in VLSI design
- 5 yrs of ASIC Synthesis and Full chip/SoC STA, timing closure expertise.
- Experienced in Cadence RTL Compiler/Genus or Synopsys DC (Design compiler DC/DC-T/DC-G) Flow.
- Improving QoR of Synthesized Netlist.
- Experienced on Cadence ETS/Tempus or Synopsys Prime Time tool. Experienced in Hierarchical and flat STA for large SoCs.
- Define and Debugging of Timing Constraints.
- Analyze and Fix Timing Issue for lower node Technology, experienced in Multi Mode Multi Corner (MCMM)timing analysis and timing closure
- Timing ECO for lower node Technology 40nm, 28nm, 20nm and below.
- Analyze and Fix Signal Integrity Issue ( Noise & Cross-talk), experienced in Tempus/Primetime
- Knowledge of Perl Scripting
- Knowledge of TCL Scripting
- Knowledge of PCI, USB, DDR interface timing closure
- Working closely with Physical design team for timing closure
- Must have good work ethic, intelligent, honest and be able to work in a fast pace, remote work environment.
- Excellent analytical skills and the ability to think out-of-the-box to develop innovative strategies.
- Ability to communicate, influence cross functional teams.
- Attention to detail, meticulous approach to problem solving. Interpersonal skills to lead a cross-divisional and cross-functional team.
- Excellent communication skills, Maturity and self-confidence, A team player with an easy-to-work-with attitude. Self-motivated, independent and resourceful problem solver.
Experience : 6-12yrs
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