Staff Recruiter at Cypress Semiconductor Corporation
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Cypress - Principal Design Engineer - RTL/Synthesis (12-20 yrs)
Principal Design Engineer responsible for the design and development of USB-PD controller SoC.
Responsibilities : Design of USB 3.0/3.1/ USB-PD controller IP and full chip integration including microarchitecture, logic design, LINT, Clock Domain Crossing Analysis, UPF, LEC, Synthesis, ATPG, overseeing all verification, backend implementation and validation aspects of the IP/Full chip etc.
Requirement : Knowledge & experience of Micro architecture, RTL, Synthesis, STA etc.. Good problem solving skills. For Logic design, experience with Logic Synthesis, Linting, CDC and DFT tools is preferred.
The candidate should be able to demonstrate the following behaviors: -
- Work effectively with both internal and external teams/customers is expected.
- Mentor other engineers and technically guide them.
- Be self-motivated with the initiative to seek constant improvements in the logic design methodologies.
- The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.
Minimum Requirements : 12+ years of relevant experience in IP/SoC design.
Must have the following :
- Proven expertise in Silicon product development preferably in micro controller space
- The ability to work as an individual and as part of a team to deliver complex IPs starting from the creation of the spec, design, verification, and finally high volume productization is a strong requirement.
- Expertise in dealing and designing with complex IP's from different sources onto the same piece of silicon.
- Understand system implications of the silicon design decisions.