17/03 Srinivas Dodla
TA-Lead at Cyient Ltd.

Views:264 Applications:29 Rec. Actions:Recruiter Actions:11

Cyient - Analog Mixed Signal Verification Engineer (3-15 yrs)

Bangalore/Hyderabad/Pune Job Code: 308420

Experience : 3-15 years

Location : Pune, Bangalore and Hyderabad

- BSEE or MSEE with Electronics /VLSI

- Hands on experience in Analog mixed signal / Mixed mode Verification

- Leading and mentoring technical team of 4 to 6 members to execute Complete verification cycle.

- Must have HANDS ON EXPERINCE simulating SPICE, SPECTRE netlists and RTL.

- Strong knowledge and experience in RTL verification test bench creation using Verilog/System Verilog and UVM.

- Tool experience AMS Designer, VCS-AMS or similar mixed signal simulators

- Lead must have experience in verifying multiple successful full chip /IP

- Domain knowledge on SERDES/USB/SATA/DDR/PCI is plus

This job opening was posted long time back. It may not be active. Nor was it removed by the recruiter. Please use your discretion.

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