Ciena - Module Lead - Fpga Designing - Packet Access Switching & Routing Platforms (6-15 yrs)
Ciena may well be the most important technology company you've never heard of. The innovations that wow us (driverless cars), and those we now take for granted (the ability to mobile-stream your favorite show) are the products of ingenuity from some brilliant and forward-thinking companies. But those companies rely on Ciena, another vanguard of innovation, to create and advance the underlying networks that bring their breakthroughs to our doorsteps. VR, AI, IOT, 5G - literally none of it would be possible without the mind-boggling technology that makes the internet itself work. For more than 25 years, Ciena has been the global leader in networking strategy, and our technology has been part of the critical infrastructure running within the most advanced companies in the world.
POSITION SUMMARY :
High speed FPGA design for Packet networking hardware acceleration of Ethernet, MPLS, and IP OAM and SAT (Service Activation Testing) protocols, statistics, packet timing, TDM circuit emulation, as well as, system glue logic for packet access switching and routing platforms.
ESSENTIAL DUTIES AND RESPONSIBILITIES :
1) Develop complex FPGA logic architecture, code, simulation, and Verification
2) Hands on bench testing of new designs for compliance to design specifications
3) Complete documentation throughout design and development cycle from theory of operation to test specifications
4) Responsible for communication and coordination with Software, Hardware, System Engineering and Validation, teams throughout the design and development cycle
5) Coordinate with technical team members design reviews, feature specifications, etc.
6) Attend meetings, report progress, and take technical leadership to troubleshoot and fix defects.
7) Provide guidance and mentoring for junior engineers hired into the team who may be tasked to perform some of the above duties.
8) Help investigate and collect information to resolve process or design issues found on a current design or in previous designs.
9) Assumes other duties as assigned
1) High speed logic design for Packet Networking equipment
2) FPGA/ASIC front end design using synthesis and simulations tools with Verilog and/or VHDL
3) Strong knowledge of using design tools for analysis, development, testing, and debug.
4) Knowledge and experience designing with Altera and Xilinx FPGAs.
5) Use of standard bench level test equipment such as oscilloscopes, logic analyzers, and other supporting equipment.
6) Strong hardware analysis, design, coding, testing, and documentation skills.
7) Ability to resolve complex issues that may require design trade-offs.
8) Excellent verbal and written communication skills.
DESIRED CHARACTERISTICS :
1) Self-starter with positive attitude
2) Team orientation, organized, and capable of independent work
3) Acumen for problem solving. Ability to lead in an environment of change - flexibility, creativity and patience
4) Ability to learn and grasp technical concepts related to products being developed
5) Able to work effectively and communicate at all levels within the Ciena workforce
EDUCATION / EXPERIENCE :
- B.E in Electronics Engineering and/or M.Tech preferred
- Minimum 6+ years of experience doing hardware design from requirements, using FPGA development tools with Verilog and/or VHDL.