Ciena - FPGA/ASIC Design Engineer (3-15 yrs)
Your experience and accomplishments really stood out to me and I would like to connect you to someone from my team to speak in details- about the exciting hardware role we have in our R&D tech center, Gurgaon.
In line with our strategic plans for growth in India, we are looking out to appoint a lead engineer in FPGA Designing who can develop complex FPGA logic architecture, code, simulation, and Verification for Packet networking hardware acceleration of Ethernet, MPLS, and IP OAM and SAT (Service Activation Testing) protocols, statistics, packet timing, TDM circuit emulation, as well as, system glue logic for packet access switching and routing platforms.
Required Skills include :
- High speed logic design for Packet Networking equipment
- FPGA/ASIC front end design using synthesis and simulations tools with Verilog and/or VHDL
- Strong knowledge of using design tools for analysis, development, testing, and debug.
- Knowledge and experience designing with Altera and Xilinx FPGAs.
- Use of standard bench level test equipment such as oscilloscopes, logic analyzers, and other supporting equipment.
- Strong hardware analysis, design, coding, testing, and documentation skills.
- Ability to resolve complex issues that may require design trade-offs.
- Excellent verbal and written communication skills.
This is key appointment for us and should you consider to discuss more on the role requirements, please share your interest with a copy of your resume and we shall arrange to speak with you soon!
Hoping to hear from you in the due course. Thank you.
PS: This role is for Gurgaon location