23/11 Madhubala Polapala
Lead - Hiring specialist at Cerium Systems

Views:400 Applications:34 Rec. Actions:Recruiter Actions:6

Cerium Systems - IP Designer - ASIC/RTL (2-18 yrs)

Bangalore Job Code: 383385

SOC/IP Design JD:

- Minimum BE/BS degree in Electrical/Electronics/Computer science required

- At least 3 to 10 years of logic design and RTL coding experience with sound knowledge on verification and implementation concepts

- Experience in networking ASIC architecture, micro-architecture development, design and debug

- Ability to code readable, maintainable, verifiable and synthesizable logic in Verilog and/or SystemVerilog

- Experience with synthesis, CDC, STA, formality, ECO process, tool flows and scripting

- Knowledge in one or more of the following areas, a definite plus

- PCIe (protocol design, link layer, integration of PHY layer)

- Ethernet (layer 2/3/4 protocols, GMII/XGMII, integration of PHY layer)

- Computer architecture/Processor fundamentals

If you are interested Kindly drop your CV.

Madhu

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