Semiconductor Recruiter at Swedium Global Services
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ASIC Verification Engineer - VMM/UVM/System Verilog (5-9 yrs)
- Good knowledge of the industry's image processing, crypto, and DMA.
- 5+ years of Verification at the module level, constrained random, VMM / UVM, reference models in the TLM / SystemC
- A resource gap for both verification and design are the team that makes the post-processing of the image processing.
- They model (SystemC / TLM), design (SystemVerilog) and verifies (SystemVerilog / UVM).
- Team is working agile with backlogs, stories and daily syncs.
- Another resource gap is in a DMA module for crypto, mostly involves the updating of an existing design.
Interested candidates share your resumes.