Semiconductor Recruiter at Swedium Global Services
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ASIC Verification Engineer - VHDL/System Verilog (10-15 yrs)
Required qualifications : Experience -10+ Years
- Experience of evaluating and creating UVM test bench architectures
- Experience of creating UVM test benches with TLM reference models
- Experience in using the System Verilog/UVM tools and methodology
- for IP verification.
- Excellent programming skills (SV, VHDL).
- Good scripting skills using e.g. Python, TCL and/or Perl.
- Knowledge about Agile ways of working is a plus.
Good to have :
- Experience from the high-speed interface, i.e. Ethernet.
- Experience in system level verification.
- Knowledge about Formal verification.
- Knowledge in programming C, C++ and System C.