Director at Nastech Consulting
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ASIC Verification Engineer - UVM/System Verilog/PCI-e (3-15 yrs)
Key words : UVM, OVM, VVM, SOC, SystemVerilog
Job Description :
- 3 years of experience in System Verilog HVL.
- 3 year of experience in OVM/UVM/VMM/Test Harness.
- Hands on experience of developing assertion, checkers, coverage and scenario creation.
- Must have executed atleast 1 SoC Verification project
- Experience in developing test and coverage plan, Verification environment and validation plan.
- Knowledge of atleast one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required.