31/10 Naga Sree
Talent Acquisition at Sventl

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ASIC Verification Engineer - System Verilog/RTL (2-6 yrs)

Bangalore Job Code: 376238

SVENTL is hiring for ASIC Verification Engineer.

Roles & Responsibilities :

- Develop verification environment and tests to perform Functional (RTL) testing at IP level and SoC Level

- Develop IP level/SoC level test plans based on the design/architectural specs.

- Coverage Analysis and Coding

- Run simulations & regressions, debug test failures to identify test case issues & RTL design issues

- Define and develop block/full chip level verification environment and its components

Required Skills:

- 2 - 6 & above years of experience in ASIC Verification and Methodologies

- Good knowledge of System Verilog, SV-OVM/SV-UVM Methodologies

- Good understanding of RTL concepts

- Good understanding of AHB/AXI protocol

- Expertise in PCI-e/ USB/ Ethernet/ Switch protocol is an added advantage

- Knowledge of Perl/TCL is Must

- Good communication skill

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