ASIC Verification Engineer - System Verilog/OVM/UVM (3-12 yrs)
Position : ASIC Verification - 3-12 Yrs
- Individually with/without guidance.
- He/She will be involved in developing assertions, RTL development/debugging and formal verification (RTL verification or tool validation).
- He/She will be involved in developing Testcases, Testplans and reviews of documents and code.
- He/She will be individually responsible for successful delivery to clients for given tasks/module of Formal Verification.
- He/She will responsible for the Client Support activities and releases of packages/patches..
- Exp in OVM,VMM,UVM
- Hands on experience in developing source code with reasonable complexity.
- Hands on experience in developing feature list, testplan and formal verification strategies from scratch.
For more details, kindly call on 9810844079 / 6393144130