Talent Acquisition at Qualcomm
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ASIC Verification Engineer - OVM/UVM (3-9 yrs)
ASIC Verification Engineer - OVM/UVM-Product Based Company- Hyderabad
Experience : 3 to 9 Yrs, Location : Hyderabad
Product Based Company
Primary responsibilities will include :
- Module / Sub-system Verification Strategy and Verification Plan development from specifications
- Development of Verification Environment (VE) and Verification Components (VC) in UVM SV
- Writing tests, sequences, functional coverage, assertions and mapping these to the Verification plan
- Functional verification of the design, debug and verification closure / signoff
Required Skills :
- An excellent knowledge of digital design verification techniques and methodologies
- Ability to determine module verification requirements from analysis of specifications
- Excellent knowledge of OVM / UVM methodology and System Verilog language.
- Experience in SoC / IP / module / Sub-system verification closure using the above methodology and language
- Hands on experience in developing complex Testbenches, tests, sequences, functional coverage and checks / assertions (SVA / PSL)
- Understanding of VHDL and/or Verilog programming languages.
Desirable Skills :
- Experience in transaction level modelling.
- Experience / knowledge of AXI4, ACE protocols.
- Formal verification techniques
- Experience with scripting language/s like Perl/Python