Talent Acquisition Member at SVENTL ASIA PEC LTD
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ASIC Verification Engineer - Embedded System (4-9 yrs)
Job Description :
- Candidates must have experience performing ASIC - Verification based on architectural/micro-architectural specification review and analysis followed with definition of - Verification requirements.
The person in this position will have the following responsibilities :
- Develop tests and test bench components from high Ievel, as well as debug of failing tests
- Verification plans, definition of functional coverage space, implementation of coverage monitors and analysis of test coverage space,
- Educational requirements for this position are a BSEE/CE minimum, MS preferred.
- 4-6 year experience in ASIC Design Verification
- Expert on SV UVM language, familiar with VHDL/Verilog, perl, C++, knowledge on AHB, Embeded System, Uart, DMA.
- Knowledge on GNSS/BT/WIFI would be a plus.
- Familiar with VCS/Verdi simulator/debugger, UPF low power simulation.