18/06 Neha Gupta

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ASIC Synthesis Engineer - VHDL/RTL (4-10 yrs)

Chennai Job Code: 456869

Basic Qualifications :

- Good understanding of VHDL or System Verilog.

- Synthesis, LEC, low power checks, Memory BIST insertion, SDC validation.

- Development of signoff quality SDC constraints and the development of power intent constraints.

- May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc.

- TCL script development in addition to running/analyzing/debugging designs.

- Hands-on with Synopsys DC/DCT/DCG/DE-Explorer.

- Hands-on with Synopsys Prime Time including SDC constraint development for complex blocks with many clock domains.

- Hands-on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development

- Experience with either RTL development or Physical Design is also a plus.

Women-friendly workplace:

Maternity and Paternity Benefits

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