01/07 Sivarama
Senior Technical Recruiter at eTeam Info Services Pvt Ltd

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ASIC Physical Design Engineer - RTL/Synthesis (4-17 yrs)

Hyderabad Job Code: 462279

We have urgent requirement for ASIC Physical design Hyderabad location.

Job description :

Structural Design: Overall Scope of work can include any of the following

- Synthesis to GDS II for blocks identified

- RTL Synthesis and STA

- Meet power target at the block level

- Floorplan based on the size/shape from FC layout construction

- Placement to meet timing targets

- Clock-tree in alignment with top-level clock construction

- Routing and post-route timing closure

- Sign-off - DRC/LVS/Caliber IR/RV, and other checks as required as defined by Intel process

- Sign-off - Timing, Formal Equivalency Verification, Power, and Noise closure as defined in Intel process

- Physical Integration blocks into level and support of SOC level integration (physical, timing, noise, etc.)

- Iterations of the above activities for early releases of RTL/netlists before the final release

- Development of block level timing constraints

- Review the results for milestones with Intel team

- Review checklist items for each milestone with Intel team

- Follow up with EDA vendor in case of tool issues

- Final sign-off reviews, checklist reviews with Intel team

- Past exposure to Intel flow/methodology, technology node 10nm & CAD Tools is must

- Preference is given to TnM contractors earlier exposed to HPG work environment

Experience - Years of experience 4 + years.

Women-friendly workplace:

Maternity and Paternity Benefits

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