17/11 Ramya Harika
Talent Acquisition Member at Sventl

Views:92 Applications:2 Rec. Actions:Recruiter Actions:2

Sventl - ASIC Design Verification Engineer - UVM/VHDL/Verilog (5-10 yrs)

Overseas/International/Singapore Job Code: 381416

SVENTL SINGAPORE is hiring for ASIC Design Verification Engineer

- Candidates must have experience performing ASIC Verification based on architectural/micro-architectural specification review and analysis followed with definition of - Verification requirements.

The person in this position will have the following responsibilities :

- Develop tests and test bench components from high Level, as well as debug of failing tests

- Verification plans, definition of functional coverage space, implementation of coverage monitors and analysis of test coverage space,

Requirements :

- Educational requirements for this position are a BSEE/CE minimum, MS preferred.

- 5-10 year experience in ASIC Design Verification

- Expert on SV UVM language, familiar with VHDL/Verilog, perl, C++, knowledge on AHB, Embeded System, Uart, DMA. Knowledge on GNSS/BT/WIFI would be a plus.

- Familiar with VCS/Verdi simulator/debugger, UPF low power simulation. Interested Candidates can apply

This job opening was posted long time back. It may not be active. Nor was it removed by the recruiter. Please use your discretion.

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