11/12 Core Edge
Director at Core Edge Solutions

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ASIC Design Verification Engineer - System Verilog/EDA/UVM (3-8 yrs)

Hyderabad Job Code: 389392

Our client US Top Notch Product -new technology start up Company starting R&D center in Hyderabad. We are looking top IIT, premium colleges background ASIC Verification & Design Engineers. Pls see the high level JD

ASIC Design Verification Engineer

Responsibilities :

- Develop verification environments for modules, subsystems, top level and FPGA

- Build models, checkers and random test frameworks using SystemVerilog and UVM

- Participate in Low power analysis (UPF), power estimation, C modeling

- Perform lint, CDC, code coverage, functional coverage

- Formal verification of modules using SVA assertions

Qualifications :

- Experience in verifying complex subsystems and ASICs

- Experience with building scalable verification environments from scratch

- Proficient at Verilog, UVM, EDA tools, scripting, automation, build, regression systems etc.

- Exposure to FPGA emulation platforms, silicon bring up, board debug

- BS/MS in EE/CS with 3+ years of experience

Work location : Hyderabad

Looking for IITs engineers

Please apply or mail to reach out.

Ganesh MR
Core Edge Solutions LLP
No.138, 7th Cross.
29th main road,( Lake road)
BTM 2nd stage, Bangalore 560076
www.coreedgesolutions.com

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